Quick answer
Designing a Custom AXI IP on Vitis is an open source FPGA project from Hackster.io, indexed by ZouIC. In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- Pablo Trujillo
- Published
- 2020-07-27
Common questions
What does Designing a Custom AXI IP on Vitis do?
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
Where does Designing a Custom AXI IP on Vitis come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/pablotrujillojuan/designing-a-custom-axi-ip-on-vitis-a0ad06.
What stack does Designing a Custom AXI IP on Vitis use?
tags AMD Xilinx, protip, beginner.
When was Designing a Custom AXI IP on Vitis published?
The source page lists 2020-07-27.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
Designing a Custom AXI IP on Vitis
Published 2020-07-27
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
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This content is sourced from Hackster.io Platform，All rights reserved by the original author. This platform only provides indexing and summaries. For detailed content, please visit the original link.