Quick answer
FPGA collects 733 projects on ZouIC. The sources include Hackster.io.
- Entries
- 733
- Sources
- Hackster.io
Common questions
How many projects does ZouIC list under FPGA?
733, each with its own detail page and a link to the original source.
Where do the FPGA entries come from?
Aggregated from Hackster.io.
DSP for FPGA: Simple FIR Filter in Verilog
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
Introduction to Using AXI DMA in Embedded Linux
This tutorial walks through an application that reads/writes data to DDR memory from the Linux userspace on the Zynq-based Arty Z7 FPGA.
FPGA-Based Edge Detection Using HLS
Leveraging HLS functions to create a image processing solution which implements edge detection (Sobel) in programmable logic.
Creating a Zynq or FPGA-Based, Image Processing Platform
Creating an image processing platform that enables HDMI input to output. This can be used as a base for HLS-based image processing demo.
A Practical Introduction to SRAM Memories Using an FPGA (I)
Let's learn everything about SRAM memories writing a controller in Verilog.
Stereo Vision and LiDAR Powered Donkey Car
Donkey Car featuring the Ultra96 board, a Raspberry Pi, FPGA accelerated stereo vision, MIPI CSI-2 image acquisition, a LiDAR sensor and AI.
Creating an FPGA-Based Low-Cost Imaging System
Not all imaging systems need to be expensive. Solutions can be created using cost optimized FPGA and CMOS image sensors directly.
Dual ARM Hello World on Zynq Using Vitis
Take full advantage of Xilinx's Zynq FPGA chip by running both of its dual ARM cores simultaneously.
UART Interface in VHDL for Basys3 Board
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
Programming Python on Zynq FPGA
This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.
Integrating Zynq PS and PL with Memory-Mapped Registers
Creating/packaging custom PL IP, then developing PS software to write/read its memory-mapped registers.
Using HLS on an FPGA-Based Image Processing Platform
Building on the Zybo Z7 image processing application. This project demonstrates using HLS with C/C++ to accelerate image processing.
Software Defined Radio on the FPGA
Radio that works with analog signal is implemented digitally on FPGA via VHDL.
Getting Started with the Kria KR260 in Vivado 2022.1
This project walks through how to build a custom hardware design for the Kria KR260 Robotics Starter Kit in Vivado 2022.1
Vitis-AI 1.3 Flow for Avnet VITIS Platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow for Avnet Vitis 2020.2 platforms.
Introduction to Digital Filters using FPGA
How to sample with High Speed ADC and DAC in FPGA and perform signal processing on the received signal
FPGA Remote Programmer
Remote programmer for Xilinx FPGAs via WiFi and Ethernet. Raspberry Pi + Jtag Pi board.
Xilinx DDS Compiler IP Tutorial on the Ultra96
An introduction to the Xilinx direct digital synthesis compiler with simple implementation on the Ultra96 V2.
Vitis-AI 1.1 Flow for Avnet VITIS Platforms - Part 1
This guide provides detailed instructions for targeting the DNNDK samples from the Xilinx Vitis-AI 1.1 flow for Avnet Vitis 2019.2 platforms
Getting Started with the Kria KR260 in PetaLinux 2022.1
This project walks through how to build a custom hardware design for the Kria KR260 Robotics Starter Kit in PetaLinux 2022.1
Use Python, Zynq and OpenCV to Implement Computer Vision
Use Python, OpenCV libraries and the PYNQ frame to implement the computer vision on Arty Z7-20 Xilinx Zynq SoC platform.
Getting Started with the Kria KV260 in Vivado 2021.1
The project walks through how to create a custom hardware project for the Kria KV260 Vision AI Starter Kit in Vivado 2021.1
Creating Xilinx Vivado board files for EBAZ4205
In this tutorial you will learn how to create Xilinx Vivado board files for your custom board.
Playing audio with an FPGA
Let´s take a look into the I2S specification and let us try to realize the first step to play audio files with an FPGA.
Vitis+PetaLinux 2022.1 & KRS 1.0 Install on Ubuntu 22.04
This project walks through the installation of Vitis and PetaLinux 2022.1 as well as KRS 1.0 on Ubuntu 22.04 Jammy Jellyfish.
Add Custom IP Modules to Vivado Block Design
See how to integrate custom RTL modules directly into Vivado block design flow.
Hello MicroBlaze on Arty-A7
See how to bring up Xilinx's soft-processor implementation, the MicroBlaze, on the Arty-A7 board.
How to Test Your Design with Vivado's Behavioral Simulation
This tutorial walks through a simple demonstration of how to deploy your testbench using Vivado's behavioral simulation.
Vitis-AI 1.2 Flow for Avnet VITIS Platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.2 flow for Avnet Vitis 2020.1 platforms.
Signal Processing with XADC and PYNQ
Creating a PYNQ image for the MicroZed 7010/20 and IO Carrier Card. Signal processing with XADC.
Two Methods of Building PetaLinux for the Ultra96
Ultra96 combines WiFi, Bluetooth & an SoC with programmable logic. Let's look at the different ways of building Linux projects aimed at it.
Face Detection and Tracking in Python on Ultra96-V2
This guide provides detailed instructions on implementing face detection and face tracking in Python on the Ultra96-V2 platform.
Getting Started with the Kria KV260 AI Vision Kit
This project walks through the out-of-the-box capabilities of the Kria K260 SoM development kit.
Training & Implementing a BNN Using Pynq
Using Pynq, we can implement an accelerated AI/ML on an FPGA without writing a line of HDL! Let's take a look at how we can this...
Vivado, Vitis, & PetaLinux 2024.1 Install on Ubuntu 22.04
An updated installation guide for the 2024.1 version of the AMD FPGA Tools on an Ubuntu 22.04 host machine.
RPi+PMOD Connector GPIO with Custom PL Design in Kria KR260
This project demonstrates how to implement a custom PL design on the KR260 utilizing its RPi & PMOD connectors.
Creating GUI App for the Ultra96 with Qt
In this tutorial you will learn how to set up Qt environment to build and debug applications created in Qt Creator for Xilinx Ultra96 board.
FPGA Based Motor Control
FPGA are ideal for precision motor control, in this project we are going to create a simple motor control application which we can build on.
Getting Started with Avnet's ZUBoard-1CG
This project walks through how to get up and running on the ZU Board using Avnet's build scripts for Vivado & PetaLinux 2022.1
Machine Learning at the Edge with Xilinx DNN Developer Kit
Programmable logic can accelerate machine learning inference. Let's take a look at how we can use the Xilinx DNNDK to do this.
Designing a Custom AXI IP on Vitis
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
Vivado, Vitis, & PetaLinux 2023.1 Install on Ubuntu 22.04
A quick write-up guide on the installation process of AMD's FPGA development tools on Ubuntu 22.04 LTS.
Using Vivado Remotely
Vivado can be run remotely on a more powerful server for improved performance while still developing on the local FPGA board
Doing Math in FPGA
FPGA are great for implementing Math, lets look at how we can do simple and complex Math in FPGA.
Vivado, Vitis, & PetaLinux 2024.2 Install on Ubuntu
A reference guide for installing the 2024.2 version AMD FPGA toolset on Ubuntu.
High Performance Imaging
Using the Genesys ZU 3EG to implement an image processing pipeline with the latest Xilinx image processing IP cores.
Implementation of an IIR filter on FPGA from scratch
In this project we are going to implement an IIR filter in an FPGA from scratch using bilinear transform and the prewarping technique.
Vivado, Vitis, & PetaLinux 2023.2 Install on Ubuntu
This project walks through how to install AMD's FPGA development tools on Ubuntu 20.04 & 22.04 LTS.
Total projects 733 · 1 / 16
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The entries on this page are all from public pages of various platforms. ZouIC only categorizes, indexes, and abstracts, and does not host code and files; The project is for developers' reference only, and the copyright and authorization belong to the original author, following their respective open source agreements.