Quick answer
Making YOLOv11 compatible with Vitis AI 3.5 and DPU is an open source FPGA project from Hackster.io, indexed by ZouIC. This article is on making YOLOv11 Pytorch model compatible with Vitis AI 3.5 and DPU IP to run the inference on AMD's MPSoC and Kria Boards.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- LogicTronix [FPGA Design + Machine Learning Company]
- Published
- 2025-08-26
Common questions
What does Making YOLOv11 compatible with Vitis AI 3.5 and DPU do?
This article is on making YOLOv11 Pytorch model compatible with Vitis AI 3.5 and DPU IP to run the inference on AMD's MPSoC and Kria Boards.
Where does Making YOLOv11 compatible with Vitis AI 3.5 and DPU come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/LogicTronix/making-yolov11-compatible-with-vitis-ai-3-5-and-dpu-aaad80.
What stack does Making YOLOv11 compatible with Vitis AI 3.5 and DPU use?
tags AMD Xilinx, tutorial, intermediate.
When was Making YOLOv11 compatible with Vitis AI 3.5 and DPU published?
The source page lists 2025-08-26.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
Making YOLOv11 compatible with Vitis AI 3.5 and DPU
Published 2025-08-26
This article is on making YOLOv11 Pytorch model compatible with Vitis AI 3.5 and DPU IP to run the inference on AMD's MPSoC and Kria Boards.
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This content is sourced from Hackster.io Platform，All rights reserved by the original author. This platform only provides indexing and summaries. For detailed content, please visit the original link.