Quick answer
Vitis HLS: Constant False Alarm Rate detector implementation is an open source FPGA project from Hackster.io, indexed by ZouIC. Implementation of Cell-Averaging (CA) and Ordered-Statistic (OS) Constant False Alarm Rate (CFAR) detector using Vitis HLS.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- Aleksei Rostov
- Published
- 2025-01-24
Common questions
What does Vitis HLS: Constant False Alarm Rate detector implementation do?
Implementation of Cell-Averaging (CA) and Ordered-Statistic (OS) Constant False Alarm Rate (CFAR) detector using Vitis HLS.
Where does Vitis HLS: Constant False Alarm Rate detector implementation come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/farbius/vitis-hls-constant-false-alarm-rate-detector-implementation-2a9aed.
What stack does Vitis HLS: Constant False Alarm Rate detector implementation use?
tags AMD Xilinx, protip, intermediate.
When was Vitis HLS: Constant False Alarm Rate detector implementation published?
The source page lists 2025-01-24.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
Vitis HLS: Constant False Alarm Rate detector implementation
Published 2025-01-24
Implementation of Cell-Averaging (CA) and Ordered-Statistic (OS) Constant False Alarm Rate (CFAR) detector using Vitis HLS
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