Quick answer
Vitis HLS: Direct Digital Synthesizer implementation is an open source FPGA project from Hackster.io, indexed by ZouIC. Implementation of fully pipelined DDS IP cores in Vitis HLS with truncated, dithered phase and Taylor serial output correction.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- Aleksei Rostov
- Published
- 2025-01-24
Common questions
What does Vitis HLS: Direct Digital Synthesizer implementation do?
Implementation of fully pipelined DDS IP cores in Vitis HLS with truncated, dithered phase and Taylor serial output correction.
Where does Vitis HLS: Direct Digital Synthesizer implementation come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/farbius/vitis-hls-direct-digital-synthesizer-implementation-9ee256.
What stack does Vitis HLS: Direct Digital Synthesizer implementation use?
tags AMD Xilinx, protip, intermediate.
When was Vitis HLS: Direct Digital Synthesizer implementation published?
The source page lists 2025-01-24.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
Vitis HLS: Direct Digital Synthesizer implementation
Published 2025-01-24
Implementation of fully pipelined DDS IP cores in Vitis HLS with truncated, dithered phase and Taylor serial output correction
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This content is sourced from Hackster.io Platform，All rights reserved by the original author. This platform only provides indexing and summaries. For detailed content, please visit the original link.