Quick answer
Vitis HLS: Matched Filter implementation is an open source FPGA project from Hackster.io, indexed by ZouIC. Time and frequency domain implementation of fully pipelined Matched Filter IP core in Vitis HLS.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- Aleksei Rostov
- Published
- 2025-01-24
Common questions
What does Vitis HLS: Matched Filter implementation do?
Time and frequency domain implementation of fully pipelined Matched Filter IP core in Vitis HLS.
Where does Vitis HLS: Matched Filter implementation come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/farbius/vitis-hls-matched-filter-implementation-62a4e9.
What stack does Vitis HLS: Matched Filter implementation use?
tags AMD Xilinx, protip, intermediate.
When was Vitis HLS: Matched Filter implementation published?
The source page lists 2025-01-24.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
Vitis HLS: Matched Filter implementation
Published 2025-01-24
Time and frequency domain implementation of fully pipelined Matched Filter IP core in Vitis HLS
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This content is sourced from Hackster.io Platform，All rights reserved by the original author. This platform only provides indexing and summaries. For detailed content, please visit the original link.