Quick answer
DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado is an open source FPGA project from Hackster.io, indexed by ZouIC. Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.
- Source
- Hackster.io
- Focus
- FPGA
- Author
- Whitney Knitter
- Published
- 2022-02-28
Common questions
What does DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado do?
Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.
Where does DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado come from?
ZouIC indexes it from Hackster.io, original page at https://www.hackster.io/whitney-knitter/dsp-for-fpga-custom-axi4-stream-fir-filter-ip-in-vivado-0d4a39.
What stack does DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado use?
tags AMD Xilinx, tutorial, advanced.
When was DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado published?
The source page lists 2022-02-28.
Indexed by ZouIC from the source platform public page, for developer reference only. Copyright and licensing stay with the author; get code and files from the original platform.
DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado
Published 2022-02-28
Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.
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