Via Current and Barrel Resistance Calculator
Works out the plated barrel cross-section from drill diameter and plating thickness, then uses the same IPC-2221 fit to estimate how much current one via carries, together with barrel resistance, drop and dissipation. Calculated in the browser; nothing is uploaded.
Result
Worked examples
Every row is produced by our Python reference implementation using the same constants and thresholds the page recalculates with; decimals go only as far as you can hand-check.
| Case | Inputs | Current per via A | Arithmetic sum for that count (not derated) A | Required cross-section area mil² | Plating thickness in mil mil | Barrel resistance per via mΩ | Drop per via at that current mV | Dissipation per via mW |
|---|---|---|---|---|---|---|---|---|
| 0.3 mm drill with 25 µm plating, outer layer, 10 °C rise | 0.3 mm · 25 µm · 10 °C · outer · 1.6 mm · 1 pcs | 1.90 | 1.90 | 39.6 | 0.984 | 1.078 | 2.051 | 3.90 |
| The same via with 18 µm plating (thin-copper process) | 0.3 mm · 18 µm · 10 °C · outer · 1.6 mm · 1 pcs | 1.48 | 1.48 | 27.9 | 0.709 | 1.530 | 2.258 | 3.33 |
| 20 × 0.3 mm vias in parallel: the total is only one via × 20, with no derating | 0.3 mm · 25 µm · 10 °C · outer · 1.6 mm · 20 pcs | 1.90 | 38.05 | 39.6 | 0.984 | 1.078 | 2.051 | 3.90 |
Where the number comes from
- d: drill diameter before plating (mil)
- t: barrel plating thickness (mil); 1 oz = 1.378 mil, 1 µm = 0.03937 mil
- k: 0.048 (outer) / 0.024 (internal), ΔT being the allowed rise
- ρ: annealed copper resistivity at 20 °C = 0.0172 Ω·mm²/m, with L taken as the board thickness
The fit reproduces the published IPC-2221 current capacity chart; it is not the standard text. All constants are listed below, please check them.
Constants: k=0.048 (outer layer) / 0.024 (internal layer) · b=0.44 · c=0.725 · 1 oz=1.378 mil=35 µm · 1 mil=0.0254 mm=25.4 µm · rho(Cu, 20 °C)=0.0172 ohm·mm²/m
What this result cannot be used to decide
This is via geometry × a temperature-rise model. It does not cover the plating uniformity declared by the fab or aspect-ratio capability, thermal-cycle and reflow reliability or the solder fill inside the hole, and it cannot know how current actually splits between several vias. Production sign-off needs a fab process confirmation and a measured temperature rise.
Frequently asked questions
How much current can one via really carry?
The dominant term is the plated barrel cross-section, A = π·(d+t)·t — so hole size and plating thickness, not the drill diameter alone. A 0.3 mm via with 25 µm plating, outer layer, 10 °C rise comes out around 1.9 A.
Can I multiply the current by paralleling vias?
Arithmetically yes, and the page reports one via × count as that sum — but do not treat it as a guaranteed value. How current splits depends on the pads and copper paths, and closely spaced vias heat each other. We deliberately do not print a "×0.7 derating" number, because that only holds once you have your own thermal boundary conditions.
What plating thickness should I enter?
Typical fab electroplated barrels land around 18-25 µm, so 25 µm is the common assumption; once you have the fab cross-section report, use the measured value. Below 15 µm the page flags that you have left the normal band.
Is the barrel resistance useful?
Negligible for small-signal paths (milliohms), but worth counting above about 1 A, or when doing current sensing and voltage-drop budgets. It is computed as R = ρL/A with L equal to the board thickness, which is a conservative upper bound since real plating is more resistive than bulk copper.
Why is the internal-layer figure lower?
The same fit with k = 0.024 for internal layers: heat stays trapped in the dielectric. In real boards, whether the via lands on a large pad or thick copper often changes the answer more than that coefficient does.
Related on this site
Data and formulas last checked：2026-11-02