All board projects
Quality open-source board projects and technical materials from CrowdSupply, Hackaday, and Hackster.io, all in one place
ASL Classification with Vitis-AI
This project is a Getting Started Guide for the ASL Classification that was presented in our Webinar series for ZUBoard.
Fix for Vitis Unified 2023.2 Launching into Blank Screen
This write-up walks through how to fix Vitis Unified IDE 2023.2 when it does nothing but launches into a blank screen in Ubuntu.
JetCar, the mini self-driving car project
The JetCar is a mini self-driving car based on the Jetson Nano. It navigates on a street map and obeys stop text and direction arrows.
Vitis-AI DPU-TRD for 2024.x with VIVADO and Kria/MPSoC
This article is on general steps and methods for creating the Vitis AI enablement project with DPU design in 2024.x tool for Kria or MPSoC.
Planck-Pi
An extremely compact, low-cost Linux development board based on the Allwinner F1C200s SoC. The PCB measures just 31×22 mm and integrates DDR + eMMC, with most GPIO exposed through an M.2 Key-A edge connector for easy stacking with carrier boards. GPL-3.0 licensed; core hardware of GeekWaedon's "Quantum Plan".
GPL-3.0
Preventing Bird Strike at Airport with KRIA KV260
Using the KV260 DPU Core & ML to Detect Birds in the Vicinity of Airport and Preventing Birds Strikes During Approach/ Landing / Take-off.
Pulse counter implemented in FPGA: hardware (VHDL) design
A fast counter that records time intervals between successive pulses such as detected photons in life sciences
XDF 2018 Mastering Programmable Logic with Xilinx SDSoC
Using proven flows for SDSoC, you will learn how to navigate SDSoC. Through hands-on labs, we will create a design for a provided platform.
Ultra96_robota
Use the camera and Vitis-AI platform to make a robot dog that can recognize people and cats.
Running Line detection app on Kria KV260(Xilinx DPU)
The idea behind this project is to use a trained neural network and try to optimise it to obtain the best hardware performance.
KV260 BIST Tutorial - Recreating with VIVADO/Vitis 2025.1
Recreating the BIST app on 2025.1 for Kria Vision Kit.
UARTLite FPGA to Linux: TTY Driver + Python Access via PCIe
Map FPGA UARTLite IP to Linux via PCIe XDMA. TTY interface and direct Python mmap access. Perfect for SDR and embedded applications!
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