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FPGAopen-source project

733Total projects
Source Distribution hackster 733
Build DDR4 Memory Tester with SKHynix H5AN8G6NCJR-VKC + FPGA
Hackster.io

Build DDR4 Memory Tester with SKHynix H5AN8G6NCJR-VKC + FPGA

A low-cost FPGA-based DDR4 memory validation platform designed to test, initialize, and analyze SK hynix H5AN8G6NCJR-VKC DDR4 SDRAM chips. T

YOLOv11 Detection + Segmentation with Versal VitisAI NPU
Hackster.io

YOLOv11 Detection + Segmentation with Versal VitisAI NPU

Enabling YOLOv11 Object Detection and Segmentation network for Vitis AI NPU for AMD Versal Platform.

GPIO Control on AUP ZU3 with PetaLinux 2022.1
Hackster.io

GPIO Control on AUP ZU3 with PetaLinux 2022.1

Build a PetaLinux 2022.1 image for the Zynq UltraScale+ AUP ZU3 and control an LED from Linux via sysfs GPIO

Running PYNQ 4.0 on the snickerdoodle black and piSmasher
Hackster.io

Running PYNQ 4.0 on the snickerdoodle black and piSmasher

AMD's PYNQ 4.0 (Ubuntu 24.04) to a Zynq-7000 board it no longer supports, and a hardware calculator demo to prove the FPGA path works

Bringing up an IMX219 video pipeline on AMD Kria KV260
Hackster.io

Bringing up an IMX219 video pipeline on AMD Kria KV260

This project walks through how to bring up an IMX219 video pipeline on an AMD Kria KV260 board.

Custom Linux driver on Zynq-7000
Hackster.io

Custom Linux driver on Zynq-7000

Writing a custom driver for an IP step by step starting from nothing and ending with interrupt handling support in the driver.

Fractions in FPGA
Hackster.io

Fractions in FPGA

Compare fixed and floating point on FPGA using a MATLAB-to-RTL IIR filter, and learn to choose Q formats and handle truncation.

MorphSense:FPGA-based Reconfigurable Sensor Network over SPE
Hackster.io

MorphSense:FPGA-based Reconfigurable Sensor Network over SPE

Reconfigurable sensor network; Deploy once, reprogram remotely. FPGA orchestrates any sensing mode over Single Pair Ethernet.

Chirp Waveform Generator Using Vitis Model Composer for FPGA
Hackster.io

Chirp Waveform Generator Using Vitis Model Composer for FPGA

From chirp equation to a parameterized FPGA architecture that generates complex I/Q waveforms by changing only bandwidth and pulse width.

vtpgZero: Portable Open-Source Video TPG for FPGA
Hackster.io

vtpgZero: Portable Open-Source Video TPG for FPGA

10 test patterns, moving box, SMPTE bars and a image overlay, in plain Verilog. Output: AXI4-Stream, FVAL/LVAL

UART on FPGA Board
Hackster.io

UART on FPGA Board

I intend to implement the UART communication protocol(the basic form of serial communication) on an FPGA. I have built the UART.

Kromi One: a new home computer with its own FPGA chipset
Hackster.io

Kromi One: a new home computer with its own FPGA chipset

Play, create and code on one fixed, fully documented machine: ARM cores plus our own FPGA chipset, drawing 1080p60 on the Kria KV260.

Custom PL Designs on Kria KV260 with AMD EDF v2025.2/v2026.1
Hackster.io

Custom PL Designs on Kria KV260 with AMD EDF v2025.2/v2026.1

This guide walks through how to build a custom HDL design into the AMD EDF Yocto project for the Kria KV260 Vision AI Starter Kit.

Total projects 733 · 16 / 16

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