Vitis-AI 1.4 Flow for Avnet VITIS Platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.4 flow for Avnet Vitis 2021.1 platforms.
YOLOv5 Quantization & Compilation with Vitis AI 3.0 for Kria
This tutorial is on Quantizing and Compiling the Ultralytics Yolov5 (Pytorch) with Vitis AI 3.0 and targeted for Kria KV260 FPGA Board.
Arm DesignStart FPGA Cortex-M3-Based Robot
Using the Arm DesignStart FPGA Cortex-M3 to control a simple wheeled robot. Also known as getting started with DesignStart FPGA & Cortex-M3.
DSP for FPGA: Using Xilinx DDS with Custom FIR
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
Vitis-AI 1.1 Flow for Avnet VITIS Platforms - Part 2
This guide provides detailed instructions for targeting the VART samples from the Xilinx Vitis-AI 1.1 flow for Avnet Vitis 2019.2 platforms
Enabling 10G Ethernet on the Xilinx KR260
This tutorial shows you how to setup a 10G SFP+ interface in a Vivado and Petalinux project for the KR260 Kria dev-kit.
OpenAMP in Xilinx MPSoC FPGA- Running Petalinux & Baremetal
This tutorial is on using OpenAMP framework for running multiple boot system on single MPSoC FPGA, as Petalinux on APU and Baremetal on RPU.
Embedded Linux on MicroBlaze
How to create and leverage embedded Linux in small FPGAs using MicroBlaze
AXI4-Lite Interface Wrapper for Custom RTL in Vivado 2021.2
This project demonstrates how to take a custom RTL module and add an AXI4-Lite interface wrapper to it for use in the Vivado block design.
Introducing Xilinx Kria™ for Vision AI Applications
Xilinx just announced Kria™, their newest product portfolio. This project takes a sneak peek at the adaptive and production ready SOM.
Kria-KR260 Petalinux 2022.2 - GPIO Tutorial
Petalinux 2022.2 GPIO project for KR260, Kria Robotics Board.
Add Peripheral Support to Kria KR260 Vivado 2022.1 Project
This project walks through the details of adding the hooks for the hardware on the KR260 carrier board in a Vivado 2022.1 project.
Back To Basics
Lets go way back and look at the basics of FPGA design and interfacing with simple actuators
MIPI Procesing with Ultra96
Creating a high performance edge processing node using the Ultra96, MIPI and DisplayPort.
SPIdev Tutorial for Zynq-7000 FPGA Devices
This project walks through how to implement and use SPI in embedded Linux via the spidev kernel on the Zynq-7000 using PetaLinux 2022.1.
Vitis-AI 1.0 Flow for Avnet Vitis Platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.0 flow for Avnet Vitis 2019.2 platforms.
Audio Processing with the Snickerdoodle
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado
Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.
Arm DesignStart FPGA Cortex-M1 Environmental Monitor
The Cortex-M1 is ideal for implementations in low-cost FPGA Spartan 7 devices. Let's look at an example project.
SDR on FPGA Part 1: ZCU102+AD9371 Setup
Setup of the ZCU102 with AD9371 FMC card for SDR applications.
Getting Started with the Arty Z7 in PetaLinux 2020.2
See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
Getting Started with the Kria KV260 in PetaLinux 2021.1
This project walks through how to create a custom embedded Linux image for the Kria KV260 Vision AI Starter Kit in PetaLinux 2021.1.
Building Ubuntu for Ultra96 FPGA
This tutorial will teach how to get Ubuntu running on U96 board.
Linux Development on the Kria KV260 with PetaLinux 2021.2
This project walks through the build of an embedded Linux image for the Kria KV260 Vision AI starter kit using PetaLinux 2021.2
Vitis-AI 2.0 Flow for Avnet VITIS Platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 2.0 flow for Avnet Vitis 2021.2 platforms.
Kria KR260-DPU-TRD-VIVADO flow (Vitis AI 3.0) Tutorial
This is DPU-TRD tutorial for Kria KR260, Robotics Starter Kit based on VIVADO flow with using Vitis AI 3.0.
AMD Spartan™ 7 FPGA Stamp Design
Creating a simple stamp containing an AMD Spartan™ 7 FPGA to design into our system
Interfacing with an FPGA from Linux on ZYNQ
Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.
Easy Machine Learning on Ubuntu with the AMD Kria KV260
Learn how to easily set up machine learning inference capabilities on the AMD/Xilinx KV260 Vision AI starter kit running Ubuntu desktop
7-Segment LED Display Hardware and VHDL Module for MiniZed
Actual PWM duty cycle on 7-segment LED display, driven by hardware (PL) and controlled by software (PS).
So you want to Design a FPGA IP Core!
Developing and Verifying a FPGA IP block requires a lot more thought than just writing the HDL. Lets take a look at how to do it!
K26 eMMC linux image programming with kv260 carrier card
Process to program Xilinx KRIA K26 production SOM non-volatile memory with Xilinx KRIA KV260 starter kit carrier card
Xilinx FPGA-HDMI1.4: You Must Know First !
This in-depth article is what you should go first to be able to work with Industry-Standard FPGA HDMI designs. Don't Miss it!
Debugging Your Custom Linux Applications Using Vitis
Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
Getting Started with the Arty Z7 in Vivado 2020.2
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
Raspberry PI Based FPGA Test System Part One
The RPI can be very powerful for testing and prototyping FPGA based solutions. Bringing up the CM5
Accelerated Design Development on Kria KR260 in Vitis 2022.1
This project walks through the creation of a custom Vitis platform and an accelerated application for the Kria KR260 Robotics Starter Kit.
Making Cora Pynq
Xilinx Pynq framework allows us to combine Python and programmable logic. Let's look at how we can create a Pynq Image for custom boards.
Verifying VHDL
When working with FPGA, before we put the design on hardware we need to be able to verify it lets take a look at how we can do this.
DSP for FPGA: Rewriting FIR Logic to Meet Timing
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
PYNQ Controlled NeoPixel LED Cube
NeoPixels are great fun to work with. LED cubes are also very visually interesting. Let's look at creating a PYNQ-controlled one!
Transfer Data between HDL and Embedded C in FPGA using DMA
This project walks through a basic structure of how to transfer data between HDL in the PL to embedded C running on a processor in an FPGA.
Yolov3 Tiny Tutorial: Darknet to Caffe for Xilinx DNNDK
This tutorial shows about "how to convert the YoloV3 Tiny" of Darknet into Caffe Framework and then implement with Xilinx DNNDK and Ultra96.
Image Processing with Arm Cortex-M1
Creating a low-cost imager solution using a Xilinx Spartan S7 and Arm Cortex-M1.
A Practical Introduction to SRAM Memories Using an FPGA (II)
Let's write an efficient SRAM controller in Verilog.
Localization Based on RF Modules Using FPGA
Find the location of a device, using multiple DWM1000-ESP8266 pairs, and an FPGA.
System Design with Vitis Unified
Creating a embedded system solution using the Vitis Unified heterogeneous system flow.
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