Ultra96v2 Linux-Based Platform in Xilinx Vitis 2020.1
This project generates and tests a Linux-based hardware platform for Ultra96v2 using the Xilinx Vitis 2020.1.
KV260 DPU-TRD Petalinux 2022.1 Vivado Flow
This project demonstrates how to build a petalinux image from BSP with DPU support using the vivado flow for KV260.
Building RISC-V for the Arty 100T
In this tutorial, we are going to look at how we can build a RISC-V, specifically the SiFive Freedom E310.
Using APU + RPU + PL on Genesys ZU
Zynq US+ is an heterogeneous device with different kind of devices inside. On this project I will show you how to use all of them together.
SPI Interface RTL for Pmod ALS (8-bit ADC) in Verilog
SPI Interface code for Pmod ALS (8-bit ADC) in Verilog is implemented from scratch,and transmitted to 7-seg display on Basys3 FPGA board.
FPGA Computer Graphics
This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.
Binary Neural Network Demonstration on Ultra96
FPGA-based Binary Neural Network acceleration used for Image Classification on the Avnet Ultra96 based on the Xilinx Zynq UltraScale+ MPSoC.
JTAG Booting an Embedded Linux image on Zynq UltraScale+
Booting Embedded Linux images on Zynq UltraScale+ MPSoC from the JTAG interface using the XSCT utility provided by Xilinx
License Plate Recognition with Vitis-AI
Vitis-AI provides a zoo of pre-built models. This project describes how to leverage these models to implement license plate recognition.
FPGA/SoC Controlled Robot Arm
Robotics are at the leading edge of Industry 4.0, AI and the Edge revolution. Let's look at how we can create an FPGA-controlled robot arm.
PetaLinux 2019.2 on Ultra96 Using BSP + Recipe Patch
Create a PetaLinux project using the new 2019.2 BSP and see how to patch an error in one of the recipe files in PetaLinux 2019.2.
Rapid Prototyping with GStreamer, Vitis AI and DeepLib
Develop Intelligent Video Processing Applications on Zynq UltraScale+ devices in minutes.
Video Mixer feature implementation on Zynq FPGA
This is reference tutorial on implementing different features of Video Mixer, mainly alpha blending and logo layer and multiple TPG layers.
ZCU102-Vitis DPU TRD - Vitis AI (3.0)
This Vitis Flow tutorial is expanded tutorial on "Vitis DPU TRD" for ZCU102 with detail steps, Build and BOOT LOG and Debug hints.
Accelerating Image Processing with PYNQ & OpenMV Cam
PYNQ is great for accelerating Python applications in programmable logic. Let's take a look at how we can use it with OpenMV camera.
Create an Image Processing with PetaLinux in 1 Hour or Less
Image processing with the Ultra96V2 and the OnSemi MIPI Mezzanine board.
Ultra96-V2 Vivado 2020.2 Basic Hardware Platform
Create a simple hardware platform using the Vivado 2020.2 GUI that can then be used for simple bare metal applications like Hello World.
A Stereo Vision System Powered by Zynq SoC with Complete RTL
A stereo vision system with the lowest grade Zynq powered by parallel computing of FPGA. RTL and other design files are presented.
Creating a Custom Kria App
When Xilinx launched Kria™, they also provided a method for quickly deploying apps. This project takes a look at creating a custom app.
PMOD IP Development for Kria KV260 using Vitis HLS
This project demonstrates how to control the PMOD I/O on the KV260 carrier board and develop IP for it using Vitis HLS.
Frequency Hopping Spread Spectrum (FHSS) System
Leveraging FPGA capabilities to design and to implement a Frequency Hopping Spread Spectrum (FHSS) System.
Lego Land Rover Defender Robot with Kria KR260
This project shows how I used the Kria KR260 & Edge Impulse to transform the Land Rover Defender Lego Technic kit into an autonomous robot.
Tracealyzer for FreeRTOS on Xilinx Zynq
A guide on how to debug your Embedded FreeRTOS applications running on an Avnet MiniZed board in an operating system aware way.
Implementing Control Algorithms with Pynq (Python)
The Xilinx Pynq framework enables us to use Python and Jupyter notebooks with FPGA designs.
Helping Out My Local Coffee Shop During COVID Using FPGAs
A summary of how I helped my favorite local coffee shop adapt to the new way of contactless business during COVID-19 using an FPGA.
Running Yolov2-tiny on KV260
This project shows how to run yolov2tiny on KV260 using the smart camera application provided by Xilinx.
FPGA Processor Expansion Module
A modular solution to expand processor capabilities using FPGA and high-speed ADC integration
![4K TPG Video Streaming in Kria KV260 [Baremetal] - Part 1](https://hackster.imgix.net/uploads/attachments/1472549/_Sd1Kg68RB6.blob?auto=compress%2Cformat)
4K TPG Video Streaming in Kria KV260 [Baremetal] - Part 1
Let's learn how to implement a standalone 4K Video Pipeline in Kria KV260 Vision AI Starter Kit
Mini But Mighty, the MiniZed and Vitis for Motor Control
How to use the MiniZed with the Vitis embedded flow for motor control applications.
Ultra96 Facial Recognition Deadbolt Using PYNQ
The title says it all! This project uses OpenCV and a convolutional neural network in PYNQ on an Ultra96 V2 to create a smart lock.
Avnet Ultra96-V2 Face Detection Tutorial
Complete an exciting face detection application within an hour on Ultra96-V2 SBC based on Xilinx Zynq UltraScale+ MPSoC.
Ping Pong Game on DE-10 FPGA Board
This game is written with in Verilog HDL. It implements VGA 640x480 resolution on the monitor using the Intel DE-10 Lite FPGA Board.
Facemask Detector
FPGA-based system that monitors facemask use through artificial intelligence, includes a thermometer and facemask dispenser.
Ultra96 FPGA-Accelerated Parallel N-Particle Gravity Sim
Demonstrating the scientific computational power of the small ZU3EG SoC by using 8 parallel floating point accelerators running at 200 MHz.
Python & PYNQ on the Snickerdoodle!
The Snickerdoodle is an SoC, with processors and programmable logic. Let's look at how we can accelerate Python with PYNQ on it!
FFT IP Core Tutorial: Vivado Simulation with Complex Numbers
How to configure, and validate a FFT IP core in Vivado using various test signals
Interfacing with AXI Peripherals in RTL
This project demonstrates how to interface with an AXI GPIO peripheral located in RTL vs in the block design in Vivado v2021.2
ROS 2 in Kria kv260 with Petalinux 2021.2
This tutorial is on how to install ROS 2 in a Petalinux 2021.2 image and launch minimal publisher/subscriber examples.
Getting Started with the TE0802
A guide for getting a TE0802 Zynq UltraScale+ MPSoC development board up and running with Vivado/Vitis 2019.2.
Weather Station & FPGA Device Talking via the IOTA Network
This is a demonstration on how a service such as a group of weather stations can influence the decisions of devices via the IOTA network.
Kria-DPU-TRD-VIVADO Flow (Vitis AI 2.0) Tutorial
This tutorial is DPU TRD based in VIVADO flow, we are using Vitis AI 2.0 along with VIVADO 2021.1 and Petalinux 2021.1
Getting Started with SP701 in Vivado 2021.2
See how to create a base hardware design for the Spartan-7 SP701 FPGA development platform in Vivado v2021.2
Live Camera Feed Webpage on the Ultra96
View a live webcam feed via a webpage implemented on the Ultra96v2.
FPGA-Based Intelligent Engine Control Unit
An intelligent way to increase fuel efficiency for Engine Control Unit by using FPGA.
Benchmarking the Kria KV260 AI Vision Starter Kit
This project demonstrates the Kria SoM's performance benchmarks and how to validate them.
Total projects 733 · 3 / 16
Related Categories
The entries on this page are all from public pages of various platforms. ZouIC only categorizes, indexes, and abstracts, and does not host code and files; The project is for developers' reference only, and the copyright and authorization belong to the original author, following their respective open source agreements.