Ultra96_for_medical_care
This project design a neural network IP interface for atrial fibrillation classification. A lot of test and ensure the advantages of it.
Bird Feeder Defender with the AMD KRIA™ KR260 Robotics Kit
I intend to address the problem of squirrels invading my bird feeders using a surveillance system designed with the KRIA™ KR260. Kit
Implementing a Configuration Memory Interface with Xilinx XC
In this project, we'll guide you through implementing a simple configuration memory interface using the XCF32P FPGA.
XSCT script for MPSoC HOST PS-USB 3.0 compliance test
XSCT script for MPSOC PS-USB 3.0 compliance test for KRIA K26 SOM development flow as an example of a simple registers manipulation tool
Using the SFP+ and GTH with Zynq Ultrascale+
How to set up the GTH transceivers for an optical 10G link, using the Transceivers Wizard and IBERT to evaluate the link quality
Running a Vitis 2025.2 Accelerator Application on the KV260
Accelerate your edge AI! Master the AMD Kria KV260 & Vitis 2025.2 workflow with this 4-step guide to running your first hardware app.
High-performance small FFT library for Versal AI Engine
The FFTs 4 Fun (FFT4F) library delivers optimized small-size FFTs (8–64 points) for AMD Versal AI Engines
19 AIE-ML model based FFT design using Vitis Model Composer
In this article we are looking at how we can create a simple 1024-point FFT using model based design with the AMD Vitis Model Composer Tool
Python-to-FPGA: MyHDL Custom IP for KR260
Create custom FPGA IP using Python/MyHDL, integrate with Vivado, and control via PYNQ—hardware design with software simplicity.
Custom PL Designs on Kria KV260 with AMD EDF v2025.2 Part 1
This guide walks through how to deploy a custom XSA on the Kria KV260 with the new EDF/Yocto workflow for AMD FPGAs.
Preparing PointPillars Network for Vitis AI NPU and Versal
Customizing the preparing the PointPillar Network to detect the objects in LiDAR point cloud for Vitis AI NPU and Versal
Project-5: Automate Kria Ubuntu SD Card Image with Docker
Automate building a custom Ubuntu SD card image for Kria with Docker—ready for boot, SSH, networking, and app development.
Synchronous LED Shifter by Clocking Wizard + VHDL Module
Run a circular LED shifter using pure PL on the Zynq MPSOC. This tutorial covers VHDL implementation, clock management, synchronized reset
Dual Address Cosine ROM Using Verilog in Vivado
The Dual Address Cosine ROM works on Discrete Cosine Transform and Quantization for dual data transfer concurrently.
Super96s Clusters - Part 3
Creating a series of modules allowing you to connect for the first time a PYNQ acceleration distribution network for edge devices U96.
Remote Control 360° Camera from KR260
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We Remote Control 360° Camera from KR260.
Leveraging Neuromorphic Event Sensors in ROS2
Utilizing the Kria KV260 and Prophesee embedded starter kit, I create a custom ROS2 package to publish 6 DOF pose of an active LED marker
Super96s Cluster - Part 2
Creating a series of modules allowing you to connect for the first time a PYNQ acceleration distribution network for edge devices U96.
20 AIE-ML code generation in Vitis Model Composer
Learn how to automate AI Engine code generation in VMC with no manual coding required. This workflow accelerates prototyping and simulation.
Distance Measurement Using Basys3
A Basys-3–based digital distance meter using sensors and FPGA logic to provide fast, accurate, real-time distance measurement
Secure Digital Access Control System
FPGA-based digital access control system from scratch using Verilog HDL and Finite State Machine (FSM) architecture, deployed on the DE1-SoC
Arty_Timer
I made a Timer which starts from 00:00:00. This module has sub module which is one_sec generation We can count min, hour, day, year.
openPCIE backplane
Need to control a bunch of End-Points from your FPGA, but don't have time to design a Root Complex card for the FPGA?!
Universal Speech Enhancement with Score Diffusion
Apply Score diffusion to improve speech signals recorded under various adverse conditions and distortions.
A Practical example of controlling FPAG from HPS - FPGA SoC
In FPGA SoC, the strength comes with having an integrated CPU Core to FPGA. These two then elevate the functions and application of FPGA.
A Synthesizable Verilog implementation of a TRNG
This project implements a hardware-based True Random Number Generator (TRNG)
Using Ada to Flash LEDs on the Zedboard
Use the Ada programming language to do simple Zynq development (PS/PL) on the Zedboard.
Custom LED Blink IP on AUP-ZU3 Zynq UltraScale+
Designed a Verilog LED IP, integrated it on AUP-ZU3 with PS clocking, handled constraints, and validated on hardware.
Running Hello World Program on MicroBlaze-V using Zybo 7000
This is a tutorial on how to get a Hello World program working on a MicroBlaze-V Softcore using the Zybo 7000 Board
Yocto & Zynq (Ubuntu 24.04.4 - Vits 2025.2)
This is indeed blinking LED for Yocto on Zynq7000. Here we create Embedded Linux for a custom Zyqn board without BSP.
Machine Alarm Detection in Factory
Machine Alarm Detection System is the detection of the machine alarm in the factory using Kria KV260 and Vitis-AI.
AMD FPGA Tools 2026.1 Install on Ubuntu
This project walks through how to install the 2026.1 version of the AMD FPGA tool suite on an Ubuntu host PC.
Space Invaders on Any Arty Board Using VHDL and Pmod VGA
Lets create a 640 × 480 Space Invaders-style game in VHDL, no processors just as the original in gates.
KRS Unleashed: 4) Vitis Workspace
This project is part of a series about KRS Unleashed, a revised version of the original KRS. This article walks through the Vitis workspace.
LabVIEW XADC Reader for Arty Z7
Read analog signals from the Arty Z7 XADC directly in LabVIEW through a custom FPGA interface for real-time data acquisition.
Forest Fire Prevention
Implementing a lightweight neural network on the KR260 edge device for precise wildfire detection.
AI Robot Arm Configuration
This project detects the mouth position and configures the robot arm using Kria KR260 Robotics Starter Kit.
Brachial Plexus Nerve Trunks Recognition
Revolutionizing brachial plexus blocks with real-time, FPGA-accelerated deep learning for accurate nerve identification in ultrasound images
ArduCAM Mini Meets the FPGA: A Pure-Logic VHDL Solution
Interfacing the ArduCAM Mini OV2640 with an FPGA using nothing but VHDL state machines: SCCB configuration, SPI capture, BRAM frame storage
Bare-metal 4k Streaming on KV260: The 2025.2 Guide Pt. 1
This is a refresh for the Vivado/Vitis v2025.2 era, and provides more details on how to set up the hardware and firmware.
Implementing SHA-256 for MicroBlaze-V with DDR + Timer
In this Tutorial, we will continue append a hardware design from the last tutorial to include DDR Memory and a Hardware Timer.
EDES 301 PocketBeagle Pong Opponent
Relax from work and sharpen your Pong skills against this (limited) AI opponent, powered by a PocketBeagle and FPGA Board.
CNN on RFSoC 4x2 with hls4ml — 11 Bugs & a Novel AXI Fix
Full hls4ml CNN pipeline on RFSoC 4x2 — every undocumented toolchain bug diagnosed and fixed, including a novel AXI DMA deadlock.
Create a Custom IP with Vitis HLS 2025.2
Build a live video pipeline on Ultra96-V2: UVC webcam through a custom HLS IP in programmable logic, then out to DisplayPort.
Generating Gaussian Noise in FPGA using LFSRs and CLT
An introduction to FPGA-friendly Gaussian noise generation, from statistical analysis to hardware IP generation.
Recreating PWM Fan Control on Kria KV260 (Custom Ubuntu)
Rebuilding PWM fan control on the Kria KV260 with a custom Ubuntu rootfs, from PL to kernel modules, device tree, and userspace tools
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