NES on MAX10 FPGA
Classic NES implementation on Altera's MAX10 using the Marutsu-CQ module.
Dual Arm core hello world: control the PL using A53 and R5
Create a dual-core ARM application using Xilinx's Vivado and Vitis tools to control programmable logic (PL) with both A53 and R5 processors.
A 0-9 Up/Down Counter in HLS
This project demonstrates the capability of high-level synthesis in describing digital systems by implementing a 0-9 Up/Down counter.
Monitoring Power on the Avnet Platforms
This guide provides instructions on how to monitor and display the PMBUS metrics on the Avnet Vitis 2020.1 platforms.
Empowering DUNE: Creating Petalinux 2022.2 OS Image for KRIA
In this tutorial, we provide the steps to create the Petalinux 2022.2 OS Image to work with KRIA KR260, Vivado 2022.2 and Petalinux 2022.2.
Fully hardwired Space Invaders in BSV
I have developed a fully hardwired Space Invaders written in BSV (Bluespec SystemVerilog) using Ultra96 FPGA board.
Vitis AI Runtime (VART) - ADAS Detection Explanation
This is explanation tutorial on ADAS detection from Vitis AI Runtime or VART from Vitis AI githb repo.
EagleEye AI: Smart Following Camera with Face Recognition
This project guides you in creating a Face-Tracking camera with IP Camera and Pan-Tilt Rotator, controlled by the KRIA™ KR260 Robotics Kit.
FPGA-based Programmable Logic Controller from DDC
PLC with an HMI operator panel. System is able to be used with real automation objects. Showcased on miniaturized, fully-functional models.
Getting Started with AMD Spartan™ 7 FPGA in PetaLinux 2023.2
This project walks through how to create an embedded Linux image for the SP701 using PetaLinux 2023.2.
Xiraffe - Smart Wildlife Observatory/Sentry on a mast
Join me in my journey to build an intelligent device for Wildlife biologists/conservationists using Xilinx Ultrascale FPGAs.
Jumpstart the KR260 with Raspberry Pi SenseHAT - Petalinux
This tutorial is beginner friendly tutorial for "Integrating Raspberry Pi SenseHAT with AMD-Xilinx Kria KR260 in Petalinux 2022.2".
KRIA kv260 petalinux build nano from source on the MPSoC
KRIA kv260 prebuilt 2021.1 linux image intelligent adaptation example (building nano editor) focused on Dandified YUM (DNF) capabilities
Pruning Yolov3 and Deploying with Vitis AI on Kria KV260
Pruning the Yolov3 with Pytorch based pruning method and Quantizing/compiling the pruned model with Vitis AI for AMD-Xilinx KV260 FPGA.
Driving Accelerators From Userspace on Ultra96
This tutorial will teach you how to program your FPGA accelerators in userspace.
LEGO brick detection using the KV260 and YoloV3-tiny
This project demonstrates the ability of the KV260 running Ubuntu to identify LEGO bricks.
Stopwatch Challenge: FPGA Fun for Conferences
Build an engaging FPGA-based stopwatch game to captivate conference attendees
Ultra96-V2 - Adding support for ROS2
This project describes how to add support for ROS2 to the Ultra96-V2.
NCO Simulation in Vivado with FCW, Phase Accumulator, and LUT
Numerically Controlled Oscillator (NCO) Simulation in Vivado: Frequency control word, Phase Accumulator and Block Memory (LUT)
Networking with the Ultra96: Port Forwarding
Access your Ultra96 from the world outside of your Wi-Fi network by using port forwarding.
PYNQ-Z2 Music Visualizer
An FPGA-based real-time audio spectrum visualizer built on the PYNQ-Z2 development board.
FSM-Based Traffic Light Controller using Verilog (Vivado Sim
This project demonstrates the design and simulation of a traffic light controller using a Finite State Machine (FSM) in Verilog HDL. The sys
Minized - PYNQ edition 2019.1
Step by step how to build working PYNQ on Minized with USB camera and WI-FI.
Genode 101: Getting started with the Zybo Z7
This is a basic tutorial about booting the Genode OS Framework on Zynq-7000-based hardware.
SWEEP 'n' PLAY
Sweep 'n' Play is a FPGA-based games consoles that offers you a new you way to play from your smartphone or tablet.
Grape detection using Vitis AI and RetinaNet
FPGA accelerated detection of bunches of grapes using object detectors in vineyards.
Importing Edge Impulse C++ Library into Vitis Workspace
This project walks through how to import a C++ library of an Edge Impulse ML model to develop accelerated applications for AMD FPGAs.
Object Detection with YOLOX + PYNQ and KR260
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We conduct 360° Object Detection with YOLOX.
![Kria KR260 + Rpi SenseHAT-LEDMatrix on Petalinux [Part II]](https://hackster.imgix.net/uploads/attachments/1557533/_lCpU1xRaOK.blob?auto=compress%2Cformat)
Kria KR260 + Rpi SenseHAT-LEDMatrix on Petalinux [Part II]
This tutorial is on integrating Raspberry Pi Sense HAT's multiple sensors and LED Matrix display with Kria KR260 in Petalinux 2022.2!
Zynq XADC tutorial, Part 3: The SW application
Tutorial on how to use Xilinx Zynq-7000 XADC. Part 3 of 3 explains how to do write a SW application in AMD Xilinx Vitis Classic.
Getting Started with the XEM8320 in Vivado 2022.1
This project walks through how to set up a base hardware design for the Artix UltraScale+ XEM8320 FPGA development board.
XADC on the Spartan 7 FPGA board
Let's learn how to get started with FPGA development. In this project we will learn about ADC on a FPGA
Benchmark Architectures of the DPU with KR260
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We compared the speeds of different DPU architectures.
Mini But Mighty motor control via builtin accelerometer
Builds on the project Mini But Mightyu, the MiniZed and Vitis for Motor Control using the built in accelerometer to control the speed.
Karp, Petalinux and Velodyne VLP16 Lidar
This project explains how to connect Velodyne VLP16 Lidar to the Kria Autonomous Robotic Platform (Karp).
Human Position Estimator For Mobile Robots
Utilize KV260's hardware acceleration to perform reliable human position estimation
AMD Versal AI Engine 2 GSPS 4K-point FFT
Custom 2 GSPS 4K FFT optimized for AMD Versal AI Engine, AI Engine ML, and AI Engine MLv2
Animate Emojis Using ZYNQ, UART and VGA
Control short animations of different emojis over VGA (480p) using UART and a ZYNQ board!
Ultra96-V2 - Combining designs into a single platform
Dealing with multiple designs can be cumbersome. This project describes how to combine multiple designs into a single platform.
Adding new ML model in VVAS & running it on KV260
This tutorial detail the steps for adding new ML model either from Vitis AI model zoo or custom model in VVAS and running it on KV260 board.
TE0711 SoM - Booting from External Flash
This project walks through how to configure the TE0711 SoM to boot from its QSPI external flash memory using the TE0701 baseboard.
Empowering DUNE: AXI IIC using Petalinux 2022.2 in KRIA
In this tutorial, we provide the steps to create the hardware design to support the AXI IIC IP and interact with I2C using Petalinux
Tria Vitis Platforms - Adding support for Hailo-8
This project describes how to add support for Hailo-8 to the Tria Vitis Platforms.
0 to 999 counter on Xilinx Spartan 6 FPGA
0 to 999 (3 digit) counter is implemented on 3 single digit 7 segment display (Common anode type) with FPGA on hardware.
Acceleration on KR260 with Vitis 24.2 (1)
Hands-on tutorial on building a Vivado (24.2 release) hardware platform for the KR260 board to be used with the Vitis flow.
Total projects 733 · 11 / 16
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