RTSP Feed Camera Source for Edge Impulse on Kria KR260
In this project, I use an RTSP camera feed with my Edge Impulse model running on my KR260 to have a wireless setup.
Using ChipScope to Debug AMD Versal Designs
In this project we will examine how we can use internal logic analysers to validate a Versal Edge Image Processing application.
Does Your FPGA Work? Let It Tell You
What if your FPGA could test itself? This interactive project checks everything from buttons to DDR memory, so you know your board is ready
Ultra96-V2 Vitis 2020.2 Test Applications
Create and run test applications from Vitis templates on Ultra96-V2.
FPGYAY 24 Days of FPGA Advent!!
Twenty Four FPGA related links, released one per day! From the 1st December to 24th
Getting Started with BLDCs on Kria KD240 + Motor Kit Part 2
This project continues with driving BLDC motors on the Kria KD240 with Motor Accessory Kit using back EMF data via an accelerated kernel.
Electronic dice using FPGA
Electronic dice or Random number generator from 1 to 6 (3 bits). The random number is displayed on common anode 7 segment display using FPGA
Arty Z7 - AI accelerator using AXI CDMA
Learn how to make FPGA AI accelerator using AXI CDMA on Arty Z7-20.
Petalinux vs. Baremetal: Run Your FPGA Video Design!
Know the difference between Petalinux and Baremetal Designs
Stereo Face Detection with the Dual Camera Mezzanine
This guide provides detailed instructions for implementing face detection on two (2) cameras using the Ultra96-V2 and Dual-Camera Mezzanine.
Vitis AI ONNX Runtime Engine (VOE) with KR260 + Python
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We introduce Vitis AI ONNX Runtime Engine (VOE) with KR260.
Lemmings Game using Verilog and FPGA
Developing Lemmings Game using Verilog and simulating it using FPGA.
FPGA Implementation of Image K-Means Clustering Algorithm
The implemented image segment uses K-Mean clustering algorithm for FPGA Devices, and it has been designed with a standard Xilinx AXI4 stream
Air Quality Sensing With Ultra96V2
Logging CO2 and TVOC to the cloud using the Ultra96 and PYNQ.
Object Detection(Yolo) with DPU-PYNQ and KR260
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We are conducting tests with DPU-PYNQ on KR260.
Vitis Hardware In the Loop
How to run Vitis Sub Systems on Hardware in the loop using Vitis.
Gesture Control of Smart Home Devices with Xilinx KV260
Compile a pretrained PyTorch model to run on a Xilinx Kria KV260 to perform gesture recognition from a USB webcam to control a FireTV stick.
Building the Ultra96-V2 PYNQ Base Overlay
A step-by-step guide on how to build the PYNQ base overlay for the Ultra96-V2.
PYNQ and Ultra96 Pulse Oximeter
Implementing a pulse oximeter using PYNQ and the Click HR4 sensor.
4 Channel TDC (Time Digital Converter) on Cmod A7 35T
Implement a 4-channel TDC on Cmod A7 35 using MicroBlaze and SRAM with 30ps rms and measurement rate of 60MSa/s
Edge Impulse on Kria KV260: Basic ML Model Development
This project walks through the basics of creating your own ML model in Edge Impulse & deploying it on the Kria KV260.
Debugging Accelerated Apps using Emulation in Vitis 2021.2
This project walks through how to set up a generic project in Vitis 2021.2 to debug FPGA accelerated applications using SW & HW emulation.
FPGA IP Core Generation with Vitis Model Composer
This tutorial shows how to generate FPGA IP cores using Vitis Model Composer, from modeling to deployment—step by step.
LAMP-FPGA: Accelerating Time Series Similarity Prediction
Predicting similar patterns in time series data on Ultra96-V2 FPGA board
PhiGent Heimdallr
This project implemented a CNN-based stereo application on KV26 SOM boards.
Self-driving Car Based on Learning from Vision Demonstration
A model car driven by KV260 and a USB camera mounted on the front.
Eclypse Z7 + Digitizer Zmod Software Design in Vitis 2022.1
This project continues with the bare metal application in Vitis for using the Digitizer Zmod on the Eclypse Z7 in a custom design.
Designing a Custom Carrier Board for AMD Kria™ SOMs Part 2
This project walks through the steps of how I designed my own custom carrier board for the AMD Kria™ K24 SOM.
Digital Clock in HLS
The goal of this project is to demonstrate the capability of HLS in designing a digital clock system.
U96-SVM - Stereo Vision Front-end for Ultra96-V2
Open-licensed hardware that gives Ultra96-V2 dual MIPI CSI and USB video class interfaces to realize a stereo vision system.
KRIA KV260-ATROVER (mini)
The KRIA KV260-ATROVER (AuTonomous ROVER) mini version - the first prototype of an autonomous self-driver rover with PYNQ
Stepper Motor Controller in High-Level Synthesis
The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA.
Concept to Prototype U96: Part Three
The final part of the project demonstrates how we create image processing pipeline in Petalinux and create a Vitis Acceleration Platform.
PMOD IP for Kria KV260 using Vivado/VitisHLS/Petalinux2022.1
This project demonstrates how to control the PMOD IO on the KV260 carrier board running Petalinux 2023.1 & develop IP for it using VitisHLS.
Floating-Point Numbers on 7-Segment Display in HLS
This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.
Designing a Custom Carrier Board for AMD Kria™ SOMs Part 1
This project walks through the steps of how I designed my own custom carrier board for the AMD Kria™ K24 SOM.
Mezzanine Board for Ultra96 "96AnalogXperience"
Many times we need from the FPGA some signals for use it as stimulus for other circuits. This board brings us 4 analog outputs for Ultra96.
Getting Started with the TE0711
See how to get the TE0711 SoM running on the TE0701 baseboard from Trenz Electronic.
PYNQ and IOP on Ultra96 Breakout
Implementing PYNQ overlay with an IOP for the Ultra96 Break Out
UART VHDL Implementation on FPGA with Host Data Exchange
Implement a UART communication protocol using VHDL on an FPGA development board, and data exchange with Python Serial Terminal
Zynqberry Zero Hardware Design in Vivado 2022.1
This project walks through the hardware design for the ZynqberryZero in Vivado 2022.1 to be able to use Raspberry Pi accessories with it.
TE0726 Zynqberry Hardware Design in Vivado 2022.1
This project walks through how to create a basic hardware design for the Zynqberry in Vivado 2022.1 to be compatible with Raspberry Pi pHATs
LED Patterns on the Arty S7 FPGA board
Use VHDL to make some cool patterns with the 4 LEDs on Digilent's Arty S7-25 FPGA board
Zynq XADC tutorial, Part 2: The HW design
Tutorial on how to use Xilinx Zynq-7000 XADC. Part 2 of 3 explains how to do the HW design in AMD Xilinx Vivado.
Getting Started with the Kria KD240 in PetaLinux 2023.2
This project walks through how to create a Linux OS for the Kria KD240 Drives Kit in PetaLinux 2023.2
Traffic Segmentation using Xilinx Vitis-AI
A real time Shibuya Crossing (Tokyo) traffic segmentation demo using Xilinx Zynq UltraScale+ MPSoC development board (Ultra96V2).
PYNQ-Z2 HDMI Usage - 4: Video Processing Seamless Switch
This post adds a toggle for the Sobel filter, ensuring the screen remains stable with no blackout.
BBM: Bridge Baby Monitor for Predictive Maintainence
Ultra96 FPGA-based platform to predict structural failure to cut costs of maintenance and also prevent disasters.
Total projects 733 · 9 / 16
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