System Design with Vitis and Versal AIE
Leveraging AMD Vitis™ Unified Software Platform capabilities to create an optimal AMD Versal solution.
Setting up FreeRTOS on Digilent Zybo Z7
This project walks through how to get started with FreeRTOS on Zynq SoCs.
Casino Craps game for FPGA
Playable craps game developed on the Digilent Nexys4 complete with dice graphics and bet keeping on the VGA monitor.
Kria KV260 FPGA ISP - Getting Started
Getting Started with Infinite-ISP, the open source image signal processor on AMD Kria KV260 AI Starter kit.
Visual SLAM on Ultra96-V2
An implementation of stereo-vision-based SLAM on Ultra96-V2 with FPGA acceleration for 10 FPS real-time operation.
Adding Wi-Fi to the Zynqberry
This tutorial covers how to use a USB Wi-Fi module commonly used with Raspberry Pi boards to add wireless capabilities to the Zynqberry.
MiniZed and Vitis for Motor Control with added HC-SR04
Extension of 'Mini But Mighty, the MiniZed and Vitis for Motor Control' project by Adam Taylor with HC-SR04 to control the speed.
Driving Motors with Encoders on the Kria KR260
This project demonstrates how to drive an N20 micro-gear motor with encoder using a Digilent HB3 motor controller PMOD with the Kria KR260.
Getting Started with BLDCs on Kria KD240 + Motor Kit Part 1
This project walks through the basics of controlling a BLDC motor using the AMD Kria™ KD240 Drives Starter kit with motor accessory pack.
DPU TRD for ZCU104
LogicTronix.com have built the "Deep Learning Processor Unit (DPU) TRD for ZCU104." We have created the VIVADO project and PetaLinux.
Arty Guessing Game
A simple guessing game using the Arty development board and a terminal emulator.
Pi OS for Zynqberry - Installing Adafruit CircuitPython
Start converging between microcontroller dev boards and FPGA dev boards by running Adafruit's CircuitPython on the Zynqberry for the PiOLED.
XDF 2018 Linux Application Development on Ultra96
This course demonstrates development tasks such as build, debug, and profile of the Linux environment on the Xilinx Zynq UltraScale+ MPSoC.
Super-Resolution with Vitis-AI on ZCU104 custom platform
This project describes how to create a custom Vitis platform for ZCU104 and run the SR app from Vitis-AI prebuilt model zoo on the platform.
FPGA-Fractals 1920x1080x60 Real-Time on USB Power
FPGA-based real-time fractal generation. Fully pipelined, dynamic resource allocation, up to 18000 MMUL/s. Float matrix math on J1B CPU.
AMD Spartan™ 7 FPGA Stamp Bring Up
A few weeks ago we designed an AMD Spartan™ 7 FPGA stamp let's look at bringing it up and its first use!
JTAG Booting Embedded Linux on Zynq SoC
Booting Embedded Linux images on Zynq-7000 SoC from JTAG interface using the XSCT utility provided by Xilinx
Introduction to Xilinx Kria AI Smart Camera Applications
This project looks at Xilinx Kria SOM Vision AI Smart Camera Application evalution on Windows machine.
Bare Metal/No-OS on Arty-Z7 in Vitis 2022.1
This project walks through no-OS development from hardware through to C code on the Zynq-based Arty-Z7 FPGA development board.
Detect, Decide, Do: CM5 + FPGA for Vision-Triggered Robotics
Edge AI meets deterministic motion — the CM5 sees a face, the FPGA makes it wave. Real-time robotics on the Tile Carrier Card
Machine Learning with Ultra96, DPU IP (3.0) and DNNDK
This tutorial is on how to create DPU (3.0) TRD for Ultra96 board, how to setup the DNNDK and test with Resnet50 & Yolo application on it.
Zynq Ultrascale+ Hello World in Vivado and Vitis
Making a project in Vivado that contains both PL and PS side. Export XSA to Vits, make Hello World application with demonstration of result
Use Tensil, TF-Lite and PYNQ to run YOLO on Ultra96 board
Show how to use Tensil’s open-source accelerator, TensorFlow Lite and Xilinx PYNQ to run YOLO model on Avnet Ultra96 development board.
Quantizing ResNet variants with Vitis-AI 3.0 & Pytorch
This tutorial detailed on Quantization steps (including PTQ, Fast-finetuning & QAT) for Renset 50, 101 & 152 in Pytorch & Vitis AI 3.0.
FPGA Vision Lab: Real-Time Frame Grabbing & Streaming
FPGA vision platform with MicroBlaze V: capture, debug, and stream MIPI camera data in real time full frames or high-speed ROI over Ethernet
Using MATLAB to Implement a Distortion Effect on Zynq
Project where we will develop an overdrive guitar effect with MATLAB and Zynq.
Creating a Base Hardware Design for the Zynqberry Zero
This project tutorial walks through the process of creating a base hardware design for the Zynqberry Zero FPGA board in Vivado.
Network programmability kit for Ultra96
Network FPGA developer framework for Ultrascale+ - 6x SFP+ mezzanine, 1U enclosure, IP cores in Verilog managed with NETCONF/YANG interface
RealSense Support for Kria KV260 PetaLinux 2021.1
Adding support for Intel RealSense Camera Technology on the Kria KV260
Ultra96-V2 - Adding support for Vitis-AI 3.0
This project describes how to add support for Vitis-AI 3.0 to the Ultra96-V2.
Point-Clouds based 3D-Object-Detection on PYNQ-DPU
With PYNQ -DPU overlay on KV260, we made 3D object detection on LiDAR point clouds more efficient than ever!
Concept to Prototype U96: Part One
Initial project for the concept to prototype using the Ultra96V2. This project creates a MIPI image processing pipeline using baremetal
Live NYC Subway Monitor App on Ultra96 FPGA
Using the Ultra96 and the MTA's General Transit Feed Specification (GTFS) see how to create a web application to track your morning commute.
Xilinx Vivado board files for Spartan Edge Accelerator - 1
Custom board files for XILINX Vivado/Vitis to speed up FPGA projects using the low-cost SEEED Studio Spartan Edge Accelerator platform
Digital Dice Roller in HLS
This project implements a digital dice roller on Basys3 board using HLS.
Final: Ultrasonic Radar Implementation on FPGA
In this project, FPGA-based ultrasonic radar screen have been developed, tested and applied. Design is made up of general and basic parts.
Update Boot Binary and Install Pynq on Kria KV260
How to update the boot binary on the Kria KV260 using the Ethernet recovery tool so Ubuntu 20.04 is more stable and installing Pynq.
AXI lite slave custom IP-Core to control Led under petalinux
This project will demonstrate how to use vivado to build a custom axi lite ip core to control a led on the PL side using petalinux.
Installing Ubuntu on the TE0802
This project walks through how to install an Ubuntu Linux distribution on the TE0802 MPSoC FPGA development board.
Ultra96V2 Playing Games
Ultra96v2 playing the Google Chrome Dino Game with no human interaction. Just web camera, servo and image processing.
Vitis Functional Simulation using Python
Functionally verifying a Vitis HLS Kernel using Python.
FPGA HW Acceleration Social Distancing Monitor
Social distance monitor using yolov3 and DPU acceleration on Ultra96v2
Vitis HLS: Fast Fourier Transform implementation
Fully pipelined implementation of FFT with fixed-point arithmetic in Vitis HLS
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