Industrial Communications with the Minized and RS485
Transferring information in a industrial application can be challenging. In this project lets look at how we can do this with a FPGA & RS485
Fixed Platform Design on Zynq-7000 in Vitis 2024.1
This project walks through how to develop software applications for the Zynq-7000 in the Vitis Unified IDE version 2024.1
Stereo Neural Inference with the Dual Camera Mezzanine
This guide provides detailed instructions for implementing stereo neural inference using the Ultra96-V2 and Dual-Camera Mezzanine.
MikroBus Xilinx -Breathalyzer
It just clicks! Make your future with the ease of Xilinx and Click boards. Measure your fun with your personal alcohol sensor on the Go!
FPGA DSP: FIR Filter with DDS Compiler in Vivado
Generate three signals with DDS compiler and implement lowpass filter in Vivado. The lowpass filter will filter the faster signal.
Air Quality Monitoring System using Nexys-4-DDR FPGA
Air Quality Monitoring using Nexys-4-DDR FPGA & MQ135 sensor for real-time, precise detection of harmful gases. Monitor and breathe cleaner
Low-Cost Precision Robotics
Let’s examine how we can develop a high performance, precision robot using a low-cost AMD Artix™ 7 FPGA controlled by Python.
Getting Started with AMD EDF on Kria KV260
This project walks through the workflow of using AMD's new EDF tools for embedded Linux development on the Kria KV260 Vision AI Starter Kit.
GNU Radio Toolkit on AXU2CGB Zynq UltraScale+ board - Part2
This project walks through how to create a Vitis 2021.2 hardware accelerator platform with GNU Radio Toolkit for AXU2CGB board made by Alinx
Slaying the DMA Dragon on the Kria KR260
Want to learn about DMA and Linux Drivers? Create your own Linux Kernel Module to transfer data between PS and PL using this learning guide.
"Ball Drop" New Year Timer with U96 & QT
Get QT up and running on the Ultra96 and create a simple new year ball drop application.
Face Swap on Zynq MPSoC: Vitis Software profiling + Vitis AI
This project describes how to find a compute intensive task in your application by profiling it and try to accelerate it on FPGA.
Getting Started with the Kria KD240 in Vitis Unified 2023.2
This project walks through how to create a software design for the Kria KD240 Drives Kit in Vitis Unified IDE 2023.2
Smart Traffic Camera – Pothole detector using Kria KV260
The pothole is an important and serious issue in India, as per statistics 30% of people die due to potholes or a sequence of events by this/
GNU Radio Toolkit on AXU2CGB Zynq UltraScale+ board - Part3
This project walks through how to create a Vitis 2021.2 hardware accelerator platform with GNU Radio Toolkit for AXU2CGB board made by Alinx
GPIO control on the Ultra96 with Vivado, PetaLinux, and mraa
What good is a robot without being able to control it? In this post, I go through custom GPIO setup & use, from Vivado to python code.
Porting Edge Impulse onto the Kria KV260 Vision AI Kit
This project demonstrates how to prep the Linux image for the Kria to be able to install Edge Impulse for Linux and connect to EI Studio.
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Kids math study AI Mate on Ultra96V2
AI on the Ultra96V2 board, for inspiring kids math study interest, playing math game such as 24 points.
Getting Started with the TE0727 in Vivado 2021.2
The ZynqberryZero deserves a revisit in Vivado 2021.2 as it requires a manual installation of its board preset files.
First hardware project with the Xilinx Kria KV260 kit
The Kria Starter kit is targeted at SW devs. Being a HW guy my first step is to alter the HW so I try to switch off the fan.
Making YOLOv11 compatible with Vitis AI 3.5 and DPU
This article is on making YOLOv11 Pytorch model compatible with Vitis AI 3.5 and DPU IP to run the inference on AMD's MPSoC and Kria Boards.
Fixed Platform Design on Zynq-7000 in Vivado 2024.1
This project walks through how to create a fixed hardware design (fixed platform) for the Zynq-7000 SoC in Vivado 2024.1.
Ultra96-V2 Vitis 2020.2 Hello World from ARM R5
Run a bare metal Hello World application on Ultra96-V2 from the ARM Cortex-R5 processor
Manage USB I2C/UART Click Board From PetaLinux in Ultra96
How to manage an axi uartlite peripheral from PetaLinux in Ultra96 board.
Implementation DPU, GPIO, and PWM for KR260
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We Implemented DPU, GPIO, and PWM for KR260.
Accelerated App Development on Kria KD240 in Vitis 2023.2
This project walks through the base workflow for accelerated application development on the Kria KD240 in Vitis Unified 2023.2
Fixed Platform Design on Zynq-7000 in PetaLinux 2024.1
This project walks through how to create an embedded Linux image for the ARM-core in the Zynq-7000 using PetaLinux 2024.1
Debugging HDL with ILAs in Vivado & Vitis 2023.2
This project walks through how to setup the Vivado & Vitis projects for debugging using integrated logic analyzers in HDL in verison 2023.2.
ADPLL Design for Transceiver
This project aims to create transmission line between two links using FPGA cards and solve the synchronization problems with ADPLL.
Vitis 2023.2 AXI4-Lite Slave Custom RTL
Creating custom RTL IP in PL and connecting this RTL code to PS via AXI4-Lite so we can send data from Zynq processor to FPGA logic
ADAS Reference Design with Xilinx MPSoC-EV
This tutorial is on "detailing the vivado and petalinux design flow" of ADAS system design for automotive application.
Radiation Effects Demonstrator in FPGA
In Space no one can hear your FPGA scream. High Reliability FPGA design teaching aid
Integrating Alexa & Ultra96
Voice control using Alexa is popular for a number of applications. This project shows how to connect an Ultra96 (Arm & FPGA) with Alexa.
Designing a carrier card for MicroZed Zynq-7000 SOM
First steps in making practical use of the Zynq-7000 System on Module
Data Center AI-VCK5000
The Xilinx® VCK5000 Versal Development Card is built on the Xilinx 7nm Versal™ ACAP.
Support Vector Machine on Zynq & ZynqMPSoC-Zybo & Ultra96v2
This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board.
FPGA Calculator (Basys3)
In this project, I made a 6-bit calculator on the Basys 3 board using the Xilinx SDK.
Illuminating Vivado ChipScope ILAs (UltraScale+)
Debugging in hardware can be challenging but in this project we are going to learn how to debug effectively in hardware.
HuGo
HuGo is a humanoid robot, created by 3D printing technique, controlled by FPGA boards using sensors, actuated by servo motors.
FIFO Design in 2026?
A simple, yet elegant Verilog-based FIFO design with detailed design steps, you should know!
Random number generator (4/8 bit)
Random number generator (4/8 bit) on FPGA using VHDL. Random binary number generation on FPGA.
Hardware acceleration in FPGA with Vivado and Vitis
Complete flow from scratch: Vivado platform, Petalinux build and hardware kernel build on Vitis, on the MYIR development board MYD-CZU4EV
Measuring Circuit Delay for FPGA Timing using the ADP3450
Using the ADP3450, this project measures amount of delay between asserting FPGA IO on base of NPN 2N3094 and LED illuminating on collector.
Real time filter compute with Pynq
In this project I'll show you how to design a real time filter coefficients compute with Pynq and Scipy library.
It Lives! Bringing Up the Ultra96V2 Breakout Board
The Ultra96 Breakout board bring up and commissioning.
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